RECONFIGURABLE FABRIC FOR SOC'S USING FUNCTIONAL I/O LEADS
ASSERTION CHECKING USING TWO OR MORE CORES
FIXING FUNCTIONAL ERRORS IN INTEGRATED CIRCUITS
METHOD TO LOCATE LOGIC ERRORS AND DEFECTS IN DIGITAL CIRCUITS
SERIAL IMPLEMENTATION OF ASSERTION CHECKING LOGIC CIRCUIT
METHOD AND SYSTEM FOR NETWORK-ON-CHIP AND OTHER INTEGRATED CIRCUIT ARCHITECTURES
COMBINED HARDWARE/SOFTWARE ASSERTION CHECKING
INTEGRATED CIRCUIT ANALYSIS SYSTEM AND METHOD USING MODEL CHECKING
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