Sawblade Ventures

Sawblade VenturesSawblade VenturesSawblade Ventures

Sawblade Ventures

Sawblade VenturesSawblade VenturesSawblade Ventures
  • Home
    • Profile
    • Technology
    • Workflow
    • Viewpoints
    • Family and Friends
    • Papers / Presentations
    • Videos
    • Manuals
    • Patents
    • About
    • Events
    • Contact
    • Bio
    • Home
    • Overview
      • Profile
      • Technology
      • Workflow
      • Viewpoints
      • Family and Friends
    • Reference
      • Papers / Presentations
      • Videos
      • Manuals
      • Patents
    • Info
      • About
      • Events
      • Contact
      • Bio
  • Home

PATENTS

USPTO

7,058,918

RECONFIGURABLE FABRIC FOR SOC'S USING FUNCTIONAL I/O LEADS

7,137,086

ASSERTION CHECKING USING TWO OR MORE CORES

7,146,548

FIXING FUNCTIONAL ERRORS IN INTEGRATED CIRCUITS

7,296,201

METHOD TO LOCATE LOGIC ERRORS AND DEFECTS IN DIGITAL CIRCUITS

7,305,635

SERIAL IMPLEMENTATION OF ASSERTION CHECKING LOGIC CIRCUIT

7,348,796

METHOD AND SYSTEM FOR NETWORK-ON-CHIP AND OTHER INTEGRATED CIRCUIT ARCHITECTURES

7,426,705

COMBINED HARDWARE/SOFTWARE ASSERTION CHECKING

7,493,247

INTEGRATED CIRCUIT ANALYSIS SYSTEM AND METHOD USING MODEL CHECKING


FOREIGN

CONTACT US


  • Home